A High-Performance Sram Memory Cell with Ldd-Tft Loads

In this paper we present a newly developed high-performance 4Mb SRAM memory cell using top-gate PMOS TFT loads with self-aligned LDDs (Lightly Doped Drain). This memory cell has both an ultra-low standby current of 0.02 pA at Vcc = 3 V and high stability of data holding.