A widely configurable EPROM memory compiler for embedded applications

An EPROM memory configurable in size and word width has been designed into a silicon compiler framework. The memory compiler software enables the hardware design to be encapsulated to facilitate re-use. The compiler supports memory densities ranging from 64 kb to 512 kb. The design is implemented in a 0.6 um 2-metal EPROM process. The 32 Kb/spl times/8 instance measures 1.32 mm/spl times/1.83 mm and at nominal process and environment (T/sub j/=25/spl deg/C, VDD=5.0 V) the simulated address access time is 29.4 nsec, read cycle time is 32.6 nsec, and power dissipation is 71.4 mW at 30 MHz operating speed. A streamlined design flow for integrating a new design into the compiler framework allowed for a three month design cycle from product definition to tapeout of the first instance.