A novel modulo 2n + 1 fused multiply-adder unit for secured VLSI architectures

There is increase in computer performance exponentially in past few decades which led to demand in low power and high speed arithmetic circuits which is highly challenging in designing of such kind of circuits. The Fused Multiply Add (FMA) is one of the most efficient designs from the arithmetic designs. This paper presents a novel FMA which is implemented by using modulo 2ⁿ + 1 adder and multiplier to achieve low power and high speed. The synthesis is carried out in RTL Complier using TSMC 130nm, 90nm, 65nm and 40nm technology files. In order to show the confidence of the proposed FMA it has been compared with existing one FMA. The results show that the proposed FMA has better performance in terms of delay, power and area.