A novel methodology for power consumption reduction in a class of DSP algorithms

In this paper a novel approach for low power realization of DSP algorithms that are based on inner product computation is proposed. Inner product computation between data and coefficients is a very common computational structure in DSP algorithms. The proposed methodology is based on an architectural transformation that reorders the sequence of evaluation of the partial products forming the inner products. The total Hamming distance of the sequence of coefficients, which are known before realization, is used as the cost function driving the reordering. The reordering of computation reduces the switching activity at the inputs of the computational units. Experimental results show that the proposed methodology leads to significant savings in switching activity and thus in power consumption.