Physical level design and analysis of fast fourier transforms using Vedic Mathematics

The objective of the paper is to design and analyze a physical level chip for Fast Fourier Transform using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics in certain fields are faster than regular mathematical computations. Implementing the idea of Vedic mathematics in designing a Fast Fourier Transform chip will improve the efficiency of calculation and will produce a less time consumption. Fast Fourier Transforms is a very important concept in various digital signal processing applications and thus timing will play a key role. The algorithm for Vedic Mathematics is developed by means of Hardware description Language (HDL) code and analyzed using design compiler tool from Synopsys, Inc.