A 12-bit, 5.5-μW single-slope ADC using intermittent working TDC with multi-phase clock signals

We propose a single-slope ADC with an intermittent operational time-to-digital converter (TDC). Applying an n-bit TDC that uses a multi-phase-clock signal reduced the conversion time by a factor of 2", achieved timing consistency, and realized robust meta-stability. However, since a TDC needs to operate continuously, it required a large dissipation power. In this study, we focus on generating the PWM signal of a single-slope ADC and apply a scheme for limiting the TDC operation period in order to reduce TDC power dissipation. We designed and fabricated a 12-bit ADC, which consists of a 6-bit TDC and 6-bit-single-slope ADC, by using a 0.18-μm CMOS process. The ADC, at 100 kS/s, consumes 5.5 μW from a 1-V supply. Its INL and DNL were −1.9/+1.9 LSB and −0.8/+0.5 LSB, respectively.