Robust design window determination for metal capacitors upon plasma damage

Design for reliability nowadays is of great importance on guaranteeing the first time right process with sufficient robustness margins. Thus it becomes increasingly popular to integrate a DFR methodology into the development flow. A common failure mechanism that can be associated with plasma charging damage (PCD) is the affected breakdown behavior that is usually not easily validated by simulations or enough silicon data. In order to achieve a fast assessment on reliability aspects, tests done at wafer level are the most preferable method to be used, especially improving the response time. In this work, we will describe the methodology used and provide examples of determining the design window on one major primitive device: metal-insulator-metal capacitors. Various layouts of different dimensions and special structures with interconnect variants designed will be assessed accordingly to check their reliability design window. It is extremely important to reduce or totally eliminate any pre-mature failures in addition to warrant the functional life span of the products using such devices. The unique interlayer construction of stacked metal capacitors induced a higher sensitivity to PCD. Violations of certain metal routing connection rules must be strictly forbidden. Such kind of recommendations in special design rules and precautions in metal routing connection circuitry can then be incorporated not only in respective application note documentations, but also implemented as DRC codes in design kit to optimize the products' yield and reliability.