NBTI modeling in analog circuits and its application to long-term aging simulations

We propose a circuit-level modeling approach for the threshold voltage shift in PMOS devices due to the negative-bias temperature instability (NBTI). The model is suitable for application in analog circuit design and reproduces the results of existing digital-stress NBTI models in the limit of two-level stress signals. It accounts for recovery effects during intervals of low stress, and it predicts a stress-pattern dependent saturation of the degradation at large operation times. Since the model can be solved numerically in an efficient way, we have direct access to the threshold voltage shift at arbitrary times, in particular to the exact solution at large operation times, without any approximation. We implement the model via the Cadence Spectre URL Finally, we make use of the model to compare the aging properties of several analog stress patterns. We furthermore present the results of an analog circuit-level NBTI simulation of a ring oscillator.