Switching pulse pattern optimisation for modular multilevel converters

Modular multilevel converters (MMCs) are widely used in different applications such as high voltage direct current (HVDC) applications. The HVDC station loss is highly related to the converter switching pulse pattern which is generated by modulation algorithm and cell selection methods. This paper formulates the switching pulse pattern generation, as a versatile optimisation problem. The problem constraints and objectives are formulated for HVDC applications and compared with similar problems in the field of computer science. To overcome the computational complexity in solving the introduced optimisation problem, a heuristic method is proposed for cell selection algorithm. The method utilizes the current level in order to obtain lossless switching at zero-current crossings. The study of the proposed method, in a time-domain simulation platform, shows that the method can reduce the switching converter losses by 60% compared to carrier-based modulation, maintaining the same capacitor voltage ripple. Although this paper focuses on HVDC, the mathematical model is applicable for any MMC application.