Thermal stability of WSi/sub 2/ polycide structures for 1 Gbit DRAMs

WSi/sub 2/ polycide structures have been studied as a function of silicide thickness, anneal temperature, and anneal ambient. Silicon inclusions and agglomeration of WSi/sub 2/ are observed during high temperature anneals (1050/spl deg/C and above), resulting in rough interfaces and an increase in sheet resistance. Enhanced low temperature oxidation of the WSi/sub 2/ results in oxide protrusions along the gate stack sidewalls, and can cause wordline-to-bitline leakage and open bitline contacts in a self-aligned contact process. Agglomeration and oxide protrusions can be minimized by using appropriate anneal conditions.