Study of Cu contamination during copper integration in a dual damascene architecture for sub-quarter micron technology

A detailed study of the copper contaminating step was performed during the integration of Cu metallization in a dual damascene architecture for sub-quarter micron CMOS technology. Dielectric deposition on copper was shown to be critical for SiO/sub 2/ contamination. Both the SiO/sub 2/ insulator and the etch-stop layer surface can be efficiently cleaned by using dilute HF before subsequent processing. However, this solution was shown not to be effective with inorganic antireflective coatings used for line level photolithography, which are contaminated during chemical mechanical polishing, so a complete removal of this film should be performed during integration.