A novel low temperature CVD/PVD Al filling process for producing highly reliable 0.175 /spl mu/m wiring/0.35 /spl mu/m pitch dual damascene interconnections in gigabit scale DRAMs

As VLSI back end of line (BEOL) wiring is scaled to 0.175 /spl mu/m dimensions and sub-0.5 /spl mu/m pitches, the challenges to conventional Al RIE BEOL processes are the etching and the reliability of tall/narrow Al lines and the oxide gap fill and planarization of such lines. Dual damascene approaches for gigascale DRAM BEOL offer advantages over conventional schemes of self planarization and simple etches. Al damascene has advantages compared to Cu damascene of being more compatible with previous technologies, limited contamination issues, cost effectiveness and filling of smaller line width/larger aspect ratio structures. However, an Al damascene approach requires advanced Al filling capabilities. In this paper, we compare the Al filling of 0.25 to 0.175 /spl mu/m/0.5 to 0.35 /spl mu/m pitch, 3.0 to 5 to 1 aspect ratio structures with a reflow Al process and a CVD/PVD Al processes. We show that a CVD/PVD Al fill process produces good electrical and reliability performance down to 0.175 /spl mu/m ground rules, while a conventional reflow Al process is potentially limited to 0.25 /spl mu/m ground rule devices. We also show that the electromigration lifetime of CVD/PVD Al damascene is far superior to that of Al RIE, alleviating the need to use Cu damascene for improved reliability. Thus, we believe that the CVD/PVD Al fill process is viable for 1 Gb dual damascene metallization schemes at least down to 0.175 /spl mu/m structures/0.35 /spl mu/m pitches and 5 to 1 aspect ratios.