A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration

A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V
cc
) of 1.8V, and a leakage current (I
LK
) below 1 fA/µm
²
under +/−2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/µm
²
, respectively, with their corresponding I
LK
below 0.48, 0.19 and 0.09 fAmp/µm
²
. Process reliability related defect density (D
0
) of the interposer HK-MiM is as low as 0.095% cm
⁻²
as judged by a 10 years lifetime breakdown voltage (V
bd
) criterion at V
cc
=3.2V. This low D
0
ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm
²
within the Si interposer. Moreover, the V
bd
tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I
LK
& V
bd
tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.