Device aware high-speed transceiver design in planar and FinFet technologies

This paper studies the interaction between devices in advanced CMOS processes and the analog circuits used in high-speed transceivers. It describes the impact of variation on the design with both active and passive devices, and devises circuit techniques to mitigate their impact on the performance of transceivers. A case study of transceiver components in 20nm planar and 16nm FinFET processes are used to illustrate the interactions. With proper design techniques, the transceiver in 20nm operates up to 16.3Gb/s and achieves measured bit error rate lower than 10
^-15
over 28dB channels.