Enhancement mode strained (1.3%) germanium quantum well FinFET (WFin=20nm) with high mobility (μHole=700 cm2/Vs), low EOT (∼0.7nm) on bulk silicon substrate

Compressively strained Ge (s-Ge) quantum well (QW) FinFETs with Si
_0.3
Ge
_0.7
buffer are fabricated on 300mm bulk Si substrate with 20nm W
_Fin
and 80nm fin pitch using sidewall image transfer (SIT) patterning process. We demonstrate (a) in-situ process flow for a tri-layer high-κ dielectric HfO
₂
/Al
₂
O
₃
/GeO
_x
gate stack achieving ultrathin EOT of 0.7nm with low D
_IT
and low gate leakage; (b) 1.3% s-Ge FinFETs with Phosphorus doped Si
_0.3
Ge
_0.7
buffer on bulk Si substrate exhibiting peak μ
_h
=700 cm
²
/V
_s
, μ
_h
=220 cm
²
/Vs at 10
¹³
/cm
²
hole density. The s-Ge FinFETs achieve the highest μ*C
_max
of 3.1×10
^-4
F/Vs resulting in 5x higher I
_ON
over unstrained Ge FinFETs.