SiC power devices for HEV/EV and a novel SiC vertical JFET

We propose a novel SiC VJFET with low feedback capacitance C
_rss
. A key feature of the proposed VJFET is the p
⁺
screen grid inserted between gate and drain electrode. The screen grid effectively reduces the C
_rss
by about 80% compared to a conventional VJFET. The lowest total power dissipation among existing SiC power devices can be achieved by the low C
_rss
. This new VJFET can be a promising candidate for a high-speed and low-loss SiC power device.