An improved CMOS offset-compensated current comparator for high speed applications

An improved CMOS current comparator suitable for use with either S/sup 2/I or S/sup 3/I switched-current cells is presented in this paper. The circuit also incorporates new design techniques to enhance both speed and resolution. A practical CMOS design is presented and simulations show operation at 80 MHz with 10 bit precision from a 3 V supply.