An oversampled A/D converter using cascaded fourth order sigma-delta modulation and current steering logic

In this paper the design and measured results of a fourth-order sigma-delta A/D converter is presented. Signal scaling technique was used to alleviate its large signal overload problem and maximize the allowable input signal level, which also increases the maximum output signal-to-noise ratio. A low noise current steering logic was used to design digital noise cancellation logic, which reduces the digital coupling noise and simplifies the circuit layout. The experimental chip was implemented with a 3 /spl mu/m CMOS technology and operated from a single 5 V power supply. With an oversampling ratio of 64, it achieves 91 dB dynamic range and 50 kHz conversion speed. The peak signal-to-noise ratio is 88 dB. The test results were bounded by the quality of the input signal source.