SILC-related effects in flash E/sup 2/PROM's-Part I: A quantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO/sub 2/ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism.