Energy-efficient parameterized 2-D separable convolution on FPGA

2-D Convolution is widely used in image and video processing applications. While prior work has focused on the impact of various trade-offs with respect to area, arithmetic resources and throughput, the impact of these on energy efficiency is not well studied. In this work, we propose an energy-efficient parameterized convolution architecture for 2-D separable kernel. Two types of algorithm mapping parameters, namely buffering scheme and level of parallelism, are used to characterize the architecture. By comparing the energy efficiency of architectures with various buffering schemes and parallelism, we demonstrate that the design strategy for high energy efficiency is different from the design strategy for high memory and area efficiency. With the optimized buffering scheme and parallelism, the energy consumption of the on-chip memory and external memory is significantly reduced while achieving high throughput. A DRAM activation schedule is also proposed to reduce the energy consumption of external memory. We implement the energy optimized architecture on a state-of-the-art FPGA for various image sizes. Our design sustains up to 61.8% of the peak energy efficiency of the device. Compared with the state-of-the-art design, our design achieves up to 34.1% energy efficiency improvement.