Managing signal, power and thermal integrity for 3D integration

Over the last several years, the buzzword in the electronics industry has been “More than Moore”, referring to the embedding of components into the package substrate and stacking of ICs and packages using wirebond and package on package (POP) technologies. This has led to the development of technologies that can lead to the miniaturization of electronic systems with coining of terms such as SIP (System in Package) and SOP (System on Package). More recently, the semiconductor industry has started focusing more on 3D integration using Through Silicon Vias (TSV). This is being quoted as a revolution in the electronics industry by several leading technologists. 3D technology, an alternative solution to the scaling problems being faced by the semiconductor industry provides a 3rd dimension for connecting transistors, ICs and packages together with short interconnections, with the possibility for miniaturization, as never before. The semiconductor industry is investing heavily on TSVs as it provides opportunities for improved performance, bandwidth, lower power, reduced delay, lower cost and overall system miniaturization. However, 3D integration poses several challenges related to managing signal, power and thermal integrity - three aspects of the problem that are pristine for ensuring system performance. In addition testing such integrated and miniaturized systems can be challenging as well. In this talk, a few approaches for managing signal, power and thermal integrity are presented in the context of 3D integration along with a few approaches for test and characterization.