A generic pixel distribution architecture for parallel video processing

I/O data distribution for neighbourhood operations processed in parallel computing dominates the multimedia video processing domain. Hardware designers are confronted with the challenge of architecture obsolescence due to the lack of flexibility to adapt the I/O system while upgrading the parallelism level. The usage of reconfigurable computing solves the problem partially with the capability of hardware partitioning according to the application requirements. Taking this aspect into consideration, we propose a generic I/O data distribution model dedicated to parallel video processing. Several parameters can be configured according to the required size of macro-block with the possibility to control the sliding step in both horizontal and vertical directions. The generated model is used as a part of the parallel architecture processing multimedia applications. We implemented our architecture on the Xilinx Zynq ZC706 FPGA evaluation board for two applications: the video downscaler (1:16) and the convolution filter. The efficiency of our system for distributing pixels among parallel IPs is demonstrated through several experiments. The experimental results show the decrease in the design effort using the code generation tool, the low hardware cost of our solution and how flexible is the model to be configured for different distribution scenarios.