A highly flexible reconfigurable system on a Xilinx FPGA

Runtime reconfigurable systems become more prevalent in numerous practical applications because these systems have a great flexibility. This paper presents a reconfigurable system implemented on Xilinx Field Programmable Gate Array (FPGA) where partial bitstream relocation (PBR), configuration memory readback and internal registers restoration techniques are supported. It can reduce a number of partial bitstreams stored in memory, save the implementation time and generally increase the flexibility of the reconfigurable system. The article describes a relocatable system creation where the relocation procedure is based on the bitstream major address modifications and design where the relocation of individual modules including their internal states is supported.