A K-band phase-locked loop in 0.18 μm CMOS technology for vital sign detection radar

In this paper, a low-power K-band phase-locked loop (PLL) for vital sign detection radar (VSDR) is presented. The proposed PLL was fabricated in 0.18 μm CMOS process. The transformer-feedback voltage-controlled oscillator (TF-VCO) is utilized to increase output swing and to alleviate noise issue. The cascoded frequency divider is adopted for low voltage and low power considerations. The measured phase-locked-loop phase noise at 20.2 GHz is -110 dBc/Hz at 10 MHz offset frequency and the corresponding reference spur is -58 dBc. The locking range covers a frequency band from 19.2-20.6 GHz. The PLL dissipated 38 mW (with buffers) at 1.8-V supply voltage and occupies the chip area of 0.46 mm
²
.