Fast and accurate technique to decompose jitter for very long pattern length waveform

Protocols such as CEI, 10G Ethernet and PCIe Gen3 are requiring very long pattern length stress signals such as PRBS-23 and PRBS-31 to claim compliance and ensure robustness. Unfortunately, there is equipment limitation to directly measure very long pattern signals especially on oscilloscopes due to memory size and signal processing power. Thus, new jitter decomposition algorithms are introduced to measure these long stress patterns through behavioral modeling [1-3]. However, there are accuracy concerns with these new measurement methodologies because of incidences of false results when users attempt to qualify or debug a circuit. This paper will explore the limitations of different jitter decomposition algorithms from major equipment vendors in the industry when measuring very long pattern length waveforms. We will also provide the measurement method and calculations required to obtain the correct jitter decomposition. Correlation of the calculated number against direct measurement using bit error rate tester (BERT) is also done to prove the hypothesis and validate accuracy of the methodology. The findings in this paper are very beneficial in assisting the industry to perform accurate jitter measurements with shorter test time to achieve robust designs as well as prevent precious resources from being spent on investigating false failures. The findings also allow companies to show that their products are tested under stringent conditions that satisfy customer requirements.