Variation study of process parameters in Trigate SOI-FinFET

This work presents the simulation of quantum transport in tri-gate (TG) silicon-on-insulator (SOI) FinFET using 3-D numerical simulation. The impact of process parameters like fin height (H
_Fin
), fin width (W
_Fin
), length of underlap (L
_un
) in both source and drain side are investigated using Sentaurus device simulator. The effectiveness and optimization of the process parameters required in SOI FinFETs to enable them catch up with the DC performance are systematically investigated. The performances such as threshold voltage (V
_th
), on current (I
_on
), off current (I
_off
), transconductance (g
_m
) and transconductance generation factor (TGF=g
_m
/I
_D
) of FinFET are analyzed. The results show for H
_Fin
/L
_g
=0.8 and W
_Fin
/L
_g
=0.6 have higher I
_on
and lower I
_off
which is more suitable for circuit applications.