A bitstream readback based FPGA test and diagnosis system

This paper presents a bitstream readback based automatic functional testing system for field-programmable gate array (FPGA) test and diagnosis. The proposed testing system physically consists of software tools in a PC and an FPGA-under-test with a communication channel in between. Hardware overhead is minimized due to no additional hardware required. Some software tools for boundary scan controlling, bitstream parsing as well as fault test and diagnosis are in-house developed. Leveraging the bitstream parsing tool, current states of D flipflops (DFFs) and configuration memory cell along with their absolute addresses can be obtained from readback bistreams and bitstream parsing library, respectively. Fault types and physical locations can be further determined by the fault test and diagnosis tool. The issue of IOB number limitations not addressed well by some previous work can be partly relieved along with reduced configuration numbers and improved diagnostic resolution. The BIST system is evaluated by testing several Xilinx series FPGAs, and experimental results are provided.