Area saved and clamp efficient multi-RC-triggered power clamp circuit for on-chip ESD protection

An improved multi-RC-triggered power clamp circuit is presented in this paper. It could save more silicon area than prior designs while clamp the VDD more efficiently. The three-stage RC-trigger circuit design can fast close up the clamp MOSFET when it is mis-triggered in a certain situation. Mis-trigger immunity down to 2µs power-up rise time is also achieved for a designed clamp MOSFET width of 1920µm.