A Q-band CMOS LNA with common source topology based on algorithmic design methodologies

This work presents a low-noise amplifier (LNA), based on algorithmic design methodologies in 0.13μm technology. Spiral inductors were used in the on-chip impedance matching networks, rather than transmission lines. This three-stage common source LNA achieves the minimum noise figure of 4.97 dB at 45 GHz with a compact chip size of 0.62 mm
²
(including all the testing pads). The 3-dB frequency bandwidth ranges from 42 to 50 GHz and the peak gain of 19 dB at 45 GHz. The whole circuit dissipates 27mW from 1.5-V supply.