Low power and high accurate dual-slope ADC using chopper stablized technique

A novel dual-slope analog to digital converter (DS ADC) using a special chopper stabilized (CHS) technique is presented and analyzed in this paper. The CHS technique aims to eliminate the 1/f noise and offset due to nonideal effects of amplifier and clock feed-through effect of switches. The use of switched-capacitor integrator and dynamic comparator is utilized for low power consumption and small silicon area. The highest resolution of the proposed DS ADC is 12 bits. The prototype ADC achieves a spurious free dynamic range (SFDR) of 86.01dB, a signal-to-noise ratio (SNR) of 73.25dB and an effective number of bits (ENOB) of 11.9 for an about 15Hz input at 150Hz sampling rate. The prototype ADC is realized with the CMOS 0.5um 2P3M technology, with the power consumption of only 1.55mW under 3.3V supply.