Ge gate-all-around FETs on Si

High performance Ge inversion (INV) and junctionless (JL) gate-all-around (GAA) FETs are demonstrated on epi-Ge layer on SOI. The anisotropic etching is used to remove the defect near the Ge/Si interface and to form gate-all-around structure. The INV and JL pGAAFETs have I
_on
of 235 μA/μm and 270 μA/μm at V
_GS
- V
_T
= -2 V and V
_DS
= -1 V, respectively, and show good subthreshold characteristics. The (111) sidewall INV nFETs show 2X enhanced I
_on
of 110 μA/μm with respect to the devices with near (110) sidewalls.