Future CMOS technology for low noise integrated circuit designs

This paper utilizes the recently defined equivalent noise sheet resistance to study the noise performance of future sub-100nm MOSFETs using strain engineering, channel engineering with III-V materials, and quantum-well structures for low-noise applications. Experimental results for devices fabricated in UMC's five different CMOS technology nodes and other published data down to 20 nm technology node are demonstrated. Strategies for the future low-noise technologies are also discussed.