10b 25 MS/s pipelined SAR ADC with dual- phase zero-crossing detector

A successive approximation register (SAR)-assisted two-stage pipeline ADC is presented, achieving low power consumption, high resolution and high speed. A dual-phase zero-crossing detector is used to replace the power-hungry OTA-based MDAC. Since the SAR architecture and zero-crossing circuit are proved to be voltage scalable, this ADC will be benefited from the technology scaling. Simulation results show that the ADC consumes 1.66mW at 25MS/s with 1.5V supply voltage. And it achieves a FoM of 91.7 fJ/conv.-step at the ENOB of 9.50b. The SNDR and SFDR are 58.94dB and 70.62dB, respectively.