Hardware implementation issues of carrier synchronization for pilot-symbol assisted bursts: A case study for DVB-RCS2

This paper investigates the exploration of frequency and phase synchronization methods for use in second generation of Digital Video Broadcasting — Return Channel via Satellite (DVB-RCS2). This new standard specifies reference bursts consisting of very limited number of known symbols and operation of turbo code decoder at extremely low Signal to Noise Ratio (SNR). The abovementioned constraints demand a careful investigation of algorithms with excellent communication performance. Regarding the hardware implementation of suited algorithms, the challenge is to achieve high throughput, low latency and low complexity. In this paper, we propose two carrier synchronization methods well suited for pilot-symbol assisted bursts of DVB-RCS2. Furthermore, we demonstrate their communication performance and derive the relationship between algorithmic parameters and the resulting hardware performance of chosen architecture. Finally, we present a flexible IP core, which can process both presented synchronization schemes in a very efficient way. Implementation complexity, throughput and latency of the architecture are analyzed on a XILINX Virtex-6 FPGA.