A low power frequency synthesizer chip with aperture phase detector and phase to analog converter

This paper presents a 0.18 μm CMOS low power frequency synthesizer with aperture phase detector (APD) and phase to analog converter (PAC) to reduce noise and power, and achieves lower reference spur. In locked state, the synthesizer can capture and compare the reference and VCO output signal directly by APD, and then PAC generates signal to control the current amplitude of charge pump. At 1.2 V supply voltage, measured results of the synthesizer shows a tuning range from 2.256 to 2.481 GHz, corresponding to 9.5%, a phase noise of -113.22 dBc/Hz at 1 MHz offset from 2.406 GHz, a power consumption of 4.5 mW, and a reference spur of the synthesizer is less than -60 dBc. Including pads, the chip area occupies 0.82 (0.941 × 0.871) mm
²
for wireless communication.