Optimized copper chemical mechanical polishing with CVD Co barrier at 14nm technology node

As device dimensions shrunk to the 14 nm node and beyond, damascene Cu/low-k high aspect ratio of interconnect schemes face extreme difficulties in achieving defect-free Cu gap-fill. The CVD Co was implemented to improve Copper interconnect performance which was deposited between the PVD Ta(N) liner barrier and the Cu seed layer to improve copper to barrier adhesion and copper gap fill. Therefore, the CMP-associated issues: metal bridge resulting from worse erosion, Cu void of metal line end, via resistance reduction and micro-scratch reduction, need to be solved because of Co barrier implementation and dimension shrinkage. In this investigation, we provide solution for several major issues of CMP at 14nm node. First, the metal bridge caused by worse erosion is formed before CMP because of dimension shrinkage. The worse erosion resulted from the low-k diminution during thermal effect of previous step which was used to define dual damascene structure. It was difficult to meet resistance target and eliminate metal bridge by over polishing at the same time. Second, there were still Cu voids around the end of metal line even though Cu gap-fill was improved by utilized Co liner. Third, the contact resistance of interface between via and metal surface increased due to the corrosion at the top corner was correlated to galvanic corrosion in-between Cu and Co barrier. Last, the micro scratch became killer defect because of fewer process tolerances of scratch depth at 14nm node and beyond. In this report, we provide solutions to fix yield loss because of metal bridge at particular pattern and also describe a failure hypothesis of integrated process. The mechanism is pattern deformed easily which weak Cu gap fill was shown at line end, but optimized CMP process can diminish void significantly. The Cu roughness treatment plays a key role in interconnection between via and bottom metal. The roughness also can be reduced by implementing a novel process for 14nm node and beyond.