A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement

This paper presents a low-area, high-efficiency hybrid 6-stage voltage multiplier by cascoding Dickson chargepumps and modified Cockcroft-Walton charge-pumps, and paralleling them with auxiliary charge-pumps. The proposed architecture obtains a good area and efficiency performance without using high-V devices or external capacitors. Implemented in a standard 0.18-μm CMOS process, the prototype provides a wide output range of 3-6V and 30-240μA load from a 1-V supply with an efficiency of 48-58% (52% at 6V). By using on-chip MOS capacitors as internal pumping capacitors, a 66% area reduction is gained. The area shrinks to 0.05mm
²
per 9× interleaved cell. The efficiency loss due to parasitics is compensated by creating auxiliary parasitic pumping paths to collect parasitic energy. With this feed-forward charge-pump, the efficiency increases extra 11%. Higher efficiency is thus measured than most reported on-chip Dickson CPs and cascoded doublers of comparable gain.