Through silicon via placement and mapping strategy for 3D mesh based Network-on-Chip

This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent placement of TSVs coupled with mapping can improve the performance significantly.