Modeling parasitic capacitances in Gallium Nitride (GaN) FET transistor

In this paper an effective method for modeling parasitic capacitances of Gallium Nitride (GaN) FET transistors is presented. The proposed method is a modification of a method that was proposed for Gallium Arsenide (GaAs) transistors. The modification consists of the computation of a constant relating to the asymmetry of the transistor when it is pinched-off. Experimental data, up to 50 GHz, show the effectiveness of the proposed method by comparing it with traditional methods.