An ASIP approach for interpolation performance enhancement in HEVC decoder

In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica processor using Tensilica instruction extension (TIE).