A 250MHz to 4GHz adaptive bias tuned PLL for low-jitter applications based on a fast response VCO oscillating cells

This article presents a low-jitter wide-range, 250MHz to 4GHz, PLL based on a fast responding VCO. The proposed VCO is controlled through two fast and slow response paths on oscillating elements. In fast section the control voltage of VCO is directly applied to a device to bypass extra current of differential pair tail device. Hence, the loop response to fast fluctuations of control voltage is speeded up and reduces the RMS jitter. An adaptive bias tuning scheme, as the slow response loop, effectively prevents passing a large bypass current from the sink device at lower operating frequencies and reduces the power consumption. The proposed PLL limits the RMS jitter to about 2ps and 300fs at 200MHz and 4GHz operating frequencies, respectively, where the 1.8v supply voltage is subjected to a peak-to-peak noise voltage of about 60mv and an input clock jitter of about 12ps. Power consumption is reduced to 4mW from otherwise 12.6mW at 200MHz operating frequency by using the proposed adaptive bias scheme. Power consumption increases to 9mW at 4GHz for 1.8v power supply voltage. The proposed PLL's area is 170μm×250μm in a 0.18μm CMOS process.