Using waveform engineering to optimize Class-F power amplifier performance in an envelope tracking architecture

Achieving optimal efficiency in FET-based power amplifiers used in envelope tracking (ET) architectures can be difficult, mainly due to the dynamic variation of drain-to-source capacitance (Cds) with applied drain voltage. If, for example class-F or inverse class-F high-efficiency modes are used, there is clearly a motivation to maintain devices in high-efficient states, over as much of the dynamic range as possible, where the operating supply voltage varies quite dramatically. In order to identify optimal matching solutions, the optimum fundamental and harmonic impedances need to be determined and understood at different drain voltages (Vds). Using time-domain waveform measurements and active harmonic load-pull at the device current generator plane, this paper analyzes the behavior of the current and voltage waveforms present at the output of a 10W high-voltage laterally diffused metal oxide semiconductor (HVLDMOS) device in an emulated ET setting. The measurement system is used to robustly engineer optimized class-F operation at different drain voltages at an operating frequency of 900MHz. A design methodology is then discussed that allows optimized power amplifier performance for different average Vds, within the operational ET supply voltage range, and the impact this has on overall efficiency.