Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS

As technology nodes approach deca-nanometer dimensions, many phenomena threaten the binary correctness of processor operation. Computer architects typically enhance their designs with reliability, availability and serviceability (RAS) schemes to correct such errors, in many cases at the cost of extra clock cycles, which, in turn, leads to processor performance variability. The goal of the current paper is to absorb this variability using Dynamic Voltage and Frequency Scaling (DVFS). A closed-loop implementation is proposed, which configures the clock frequency based on observed metrics that encapsulate performance variability due to RAS mechanisms. That way, performance dependability and predictability is achieved. We simulate the transient and steady state behavior of our approach, reporting responsiveness within less than 1 ms. We also assess our idea using the power model of real processor and report a maximum energy overhead of roughly 10 percent for dependable performance in the presence of RAS temporal overheads.