Design of H.264 Video Decoding IP Core on FPGA

This paper presents a design of IP core used in H.264 video decoding based on FPGA, which optimizes the SOPC system with NIOS II software processor being the kernel. This design contributes to the optimization of hardware within which the CAVLC entropy decoding and intra-prediction module locate. The methodology of hardware acceleration to IP core, as is proved by the experiment in this paper and compared to the H.264 decoding method exerted by NIOS II software without the assistance of hardware acceleration, shrinks the span of time consumed by decoding and realizes the real-time video playing using H.264 decoder based on FPGA.