1T Capacitor-Less DRAM Cell Based on Asymmetric Tunnel FET Design

In this work we propose and demonstrate the use of a Tunnel FET (TFET) as capacitorless DRAM cell based on TCAD simulations and experiments. We report more experimental results on Tunnel FETs implemented as a double-gate (DG) fully-depleted Silicon-On-Insulator (FD-SOI) devices. The Tunnel FET based DRAM cell has an asymmetric body and a partial overlap of the top gate (L
_G1
) with a total overlap of the back gate over the channel region (L
_G2
). A potential well is created by biasing the back gate (V
_G2
) in accumulation while the front gate (V
_G1
) is in inversion. Holes from the p+ source are injected by the forward-biased source/channel junction and stored in the electrically induced potential well. Programming conditions and related transients are reported and the role of temperature is investigated.