Scalable image sensor/processor architecture with frame memory buffer and 2-D cellular neural network

Compact, high computing power systems become feasible with significant progress in the research and development of advanced computing architecture and array processing. Scalable image sensor array processor with frame memory buffer and cellular neural network (CNN) for nearest neighbor interaction has been developed in a 0.5 /spl mu/m HP CMOS technology. The CNN with analog programmable weights was constructed with compact mixed-signal VLSI circuit components in the current-mode techniques. The low voltage, low power operation is supported with the current mode scheme which scales well with the supply voltage. VLSI design of a variable gain neuron circuit can be incorporated into the prototype to realize the optimal solution capability using hardware annealing.