Analysis of the Back-Gate Effect in Normally OFF p-GaN Gate High-Electron Mobility Transistor

This paper discusses the impact of the back-gate bias on the dc, low-frequency noise, and dynamic behavior characteristics of a p-GaN gate high-electron mobility transistor on silicon substrate. This paper is investigated to understand the physical mechanisms of the back-gate terminal modulation of normally OFF GaN power devices. When a negative backgate bias V
_B
voltage is applied, the 2-D electron gas channel will get closer to AlGaN/GaN heterointerface and interface scattering, such as interface roughness and alloy-disorder scattering will increases significantly, which may be responsible for the increased ON-state resistance (R
_ON
). Meanwhile, the opportunity for the capture of carriers by deep-level traps is reduced and the low-frequency noise is thereby suppressed. Under positive V
_B
bias, R
_ON
can be reduced but, according to capacitance-voltage measurements and carrier fluctuations extracted from the low-frequency noise spectra, the transported carriers are obviously trapped by the deep-level.