Area-efficient single-stage configuration for implantable neural recording amplifiers based on back attenuation

A new single-stage configuration is proposed for low-power low-noise amplifiers designed for neural recording applications. Employing an attenuator in the feedback loop around the amplifier, both upper and lower cut-off frequencies of the amplifier (f
CL
and f
CH
) are realized using much smaller capacitances as compared with those used in other neural amplifiers available in the literature. This leads to both considerable reduction in the consumed silicon area and increase in the input impedance of the amplifier. Furthermore, the high-resistance nonlinear pseudo-resistor traditionally used to achieve a very small f
CL
is replaced by a transconductance attenuator. Designed and simulated in a 0.18-µm CMOS process, the amplifier consumes 19.8 µW from a 1.8-V supply.