State and Angular Dependence of Single-Event Upsets in an Asymmetric RC-Hardened SRAM Using Deep Trench Capacitors

A marked state dependence and significant reduction in SEU cross section with even small increases in incident angle are reported in an asymmetric RC-hardened 90 nm CMOS SRAM. The effects are attributable to the bias dependence and high aspect ratio of the deep trench capacitor sidewall depletion region, exacerbated by process-induced boron depletion. The asymmetric implementation, using capacitive hardening in only one leg of the SRAM cell, led to the appearance of the effect in experimental results.