Re-configurable optimized area CTC codec for wireless applications

Today's need of wireless communication is undergoing astounding growth in day to day process. The quality of wireless communication must be enhanced with reduced cost. A coding system is required which can provide high data rate with error free communication and reduced area utilization. Among various error correcting codes, the turbo codes known as Parallel Convolutional Concatenated Code (PCCC) provides performance improvement with miniaturization in communication system. In this paper, an area efficient Convolutional Turbo Codec of constraint length 3 is proposed. To reduce the area consumption, the proposed turbo decoder uses a single SISO (Soft Input Soft Output) decoder architecture. In SISO decoders SOVA (Soft Output Viterbi Algorithm) is used as a decoding algorithm. It is based on two step algorithm. The proposed codec design has been synthesized on Xilinx Virtex-4 (xc4vlx25-ff676-10) FPGA. The performance of proposed Turbo Codec compared for FPGAs in terms of number of slices, slice flip-flops and LUTs. The Synthesis result shows 7% improvement in the utilized no. of slices and slice flip-flop of proposed encoder and approximately 3% improvement in the utilized number of slice flip-flop of the proposed decoder. The Simulink model for proposed CTC encoder and decoder is generated accordingly.